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1 isl6420b advanced single synchronous buck pulse-width modulation (pwm) controller isl6420b the isl6420b simplifies the implementation of a complete control and protection scheme for a high-performance dc/dc buck converter. it is designed to drive n-channel mosfets in a synchronous rectified buck topology. the isl6420b integrates control, output adjustment, monitoring and protection functions into a single package. additionally, the ic features an external reference voltage tracking mode for externally referenced buck converter applications and ddr termination supplies, as well as a voltage margining mode for system testing in networking dc/dc converter applications. the isl6420b provides simple, single feedback loop, voltage mode control with fast transient response. the output voltage of the converter can be precisely regulated to as low as 0.6v. the operating frequency is fully adjustable from 100khz to 1.4mhz. high frequency operation offers cost and space savings. the error amplifier features a 15mhz gain-bandwidth product and 6v/s slew rate that enables high converter bandwidth for fast transient response. the pwm duty cycle ranges from 0% to 100% in transient conditions. selecting the capacitor value from the enss pin to ground sets a fully adjustable pwm soft-start. pulling the enss pin low disables the controller. the isl6420b monitors the output voltage and generates a pgood (power good) signal when soft-start sequence is complete and the output is within regulation. a built-in overvoltage protection circuit prevents the output voltage from going above typically 115% of the set point. protection from overcurrent conditions is provided by monitoring the r ds(on) of the upper mosfet to inhibit the pwm operation appropriately. this approach simplifies the implementation and improves efficiency by eliminating the need for a current sensing resistor. features ?operates from: - 4.5v to 5.5v input - 5.5v to 28v input ? 0.6v internal reference voltage - 2.0% reference accuracy ? resistor-selectable switching frequency - 100khz to 1.4mhz ? voltage margining and external reference tracking modes ? output can sink or source current ? lossless, programmable overcurrent protection - uses upper mosfet?s r ds(on) ? programmable soft-start ? drives n-channel mosfets ? simple single-loop control design - voltage-mode pwm control ? fast transient response - high-bandwidth error amplifier - full 0% to 100% duty cycle ? extensive circuit protection functions - pgood, overvoltage, overcurrent, shutdown ? diode emulation during startup for pre-biased load applications ? offered in 20 ld qfn and qsop packages ? qfn (4x4) package - qfn compliant to jedec pub95 mo-220 qfn -quad flat no leads - product outline - qfn near chip scale package footprint; improves pcb efficiency, thinner in profile ? pb-free (rohs compliant) applications ? power supplies for microprocessors/asics - embedded controllers - dsp and core processors - ddr sdram bus termination ? ethernet routers and switchers ? high-power dc/dc regulators ? distributed dc/dc power architecture ? personal computer peripherals ? externally referenced buck converters december 4, 2009 fn6901.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6901.1 december 4, 2009 ordering information part number (notes 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6420biaz 6420b iaz -40 to +85 20 ld qsop m20.15 isl6420biaz-tk (note 1) 6420b iaz -40 to +85 20 ld qsop (tape and reel) m20.15 isl6420birz 64 20birz -40 to +85 20 ld 4x4 qfn l20.4x4 ISL6420BIRZ-TK (note 1) 64 20birz -40 to +85 20 ld 4x4 qfn (tape and reel) l20.4x4 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device in formation page for isl6240b for more information on msl please see techbrief tb363 . pin configurations isl6420b (20 ld qfn) top view isl6420b (20 ld qsop) top view gpio2 gpio1/refin ocset vmset/mode boot ugate phase pvcc lgate vin sgnd rt fb refout vcc5 1 2 3 4 5 678910 15 14 13 12 11 20 19 18 17 16 pgnd cdel pgood enss comp 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 cdel pgnd lgate pvcc phase ugate gpio2 boot gpio1/refin ocset pgood comp fb rt enss sgnd vin vcc5 vmset/mode refout isl6420b
3 fn6901.1 december 4, 2009 block diagram boot ugate ep (qfn only) phase enss gpio2 fb comp vmset/mode gpio1/refin pgnd lgate ea pwm pvcc vcc5 gate control logic internal series rt refout cdel pgood pgood comp vin linear ocset 100 a ov/uv comp oscillator comp internal sgnd power-on reset (por) 10 a ssdone ssdone enss ssdone fault logic otp ss v ref 0.6v voltage margining control isl6420b
4 fn6901.1 december 4, 2009 typical 5v input dc/dc application schematic typical 5.5v to 28v input dc/dc application schematic + - rt fb comp enss ref + - osc vin 5v 10% c 1 l 1 c 10 0.1f ugate ocset phase boot d 1 q 1 c 7 r 2 r 4 c 12 c 11 c 2 c 6 c 5 r 1 c 9 lgate q 2 v out r 3 monitor and protection + - gpio1/refin gpio2 refout cdel pgnd pvcc sgnd vcc5 c 4 c 3 pgood r 5 c 8 r 6 c 13 voltage margining enabled with internal v ref see page 12 for more details vmset/mode + - rt fb comp enss ref + - osc vin 5.5v to 28v c 1 l 1 c 10 0.1f ugate ocset phase boot d 1 q 1 c 7 r 2 r 4 c 12 c 11 c 2 c 6 c 5 r 1 c 9 lgate q 2 v out r 3 monitor and protection + - gpio1/refin gpio2 refout cdel pgnd pvcc sgnd vcc5 c 4 c 3 pgood r 5 c 8 r 6 c 13 voltage margining enabled with internal v ref see page 12 for more details vmset/mode isl6420b
5 fn6901.1 december 4, 2009 typical 5v input dc/dc application schematic typical 5.5v to 28v input dc/dc application schematic rt fb comp enss ref osc vin 5v 10% c 1 l 1 c 9 ugate ocset phase boot d 1 q 1 c 7 r 2 r 4 c 11 r 5 c 10 c 2 c6 c 5 r 1 c 8 lgate q 2 2.5v/1.25v r 3 monitor and protection + - + - gpio2 cdel pgnd pvcc sgnd vcc5 c 4 c 3 pgood configuration for ddr termination/externally referenced tracking applications vcc5 c 12 refout 1.25v v ref to refin of vtt supply gpio1/refin <-- v ref = vddq/2 vmset/mode rt fb comp enss ref osc vin 5.5v to 28v c 1 l 1 c 9 ugate ocset phase boot d 1 q 1 c7 r 2 r 4 c 11 r 5 c 10 c 2 c 6 c 5 r 1 c 8 lgate q 2 2.5v/1.25v r 3 monitor and protection + - + - cdel pgnd pvcc sgnd vcc5 c 4 c 3 pgood configuration for ddr termination/extern ally referenced tracking applications vcc5 gpio2 refout 1.25v v ref to refin of vtt supply gpio1/refin <-- v ref = vddq/2 vmset/mode isl6420b
6 fn6901.1 december 4, 2009 typical 5v input dc/dc application schematic typical 5.5v to 28v input dc/dc application schematic + - rt fb comp enss ref + - osc vin 5v 10% c 1 l 1 c 10 0.1f ugate ocset phase boot d 1 q 1 c 7 r 2 r 4 c 12 c 11 c 2 c 6 c 5 r 1 c 9 lgate q 2 v out r 3 monitor and protection + - gpio1/refin gpio2 refout cdel pgnd pvcc sgnd vcc5 c 4 c 3 pgood r 5 c 8 c13 use internal v ref with no see page 12 for more details voltage margining vmset/mode + - rt f b comp enss ref + - osc vin 5.5v to 28v c 1 l 1 c 10 0.1f ugate ocset phase boot d 1 q 1 c 7 r 2 r 4 c 12 c 11 c 2 c 6 c 5 r 1 c 9 lgate q 2 v out r 3 monitor and protection + - gpio1/refin gpio2 refout cdel pgnd pvcc sgnd vcc5 c 4 c 3 pgood r 5 c 8 c 13 use internal v ref with no see page 12 for more details voltage margining vmset/mode isl6420b
7 fn6901.1 december 4, 2009 absolute maximum ratings (note 4) thermal information bias voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . +30v boot and u gate pins . . . . . . . . . . . . . . . . . . . . . . . . . +36v thermal resistance (typical) ja (c/w) jc (c/w) qfn package (notes 5, 6) . . . . . . . 47 8.5 qsop package (note 5) . . . . . . . . 90 na maximum junction temperature (plastic package) . . +150c maximum storage temperature range . . . -65c to +150c ambient temperature range . -40c to +85c (for ?i? suffix) junction temperature range . . . . . . . . . . -40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. all voltages are with respect to gnd. 5. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: vin = 12v, pvcc shorted with vcc5, t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 12) typ max (note 12) units vin supply input voltage range 5.6 12 28 v vin supply current shutdown current (not e 7) enss = gnd - 1.4 - ma operating current (notes 7, 8) - 2.0 3.0 ma vcc5 supply (notes 8, 9) input voltage range vin = vcc5 for 5v configuration 4.5 5.0 5.5 v output voltage vin = 5.6v to 28v, i l = 3ma to 50ma 4.5 5.0 5.5 v maximum output current vin = 12v 50 - - ma power-on reset rising vcc5 threshold vin co nnected to vcc5, 5v input operation 4.310 4.400 4.475 v falling vcc5 threshold 4.090 4.100 4.250 v uvlo threshold hysteresis 0.16 - - v pwm converters maximum duty cycle f sw = 300khz 90 96 - % minimum duty cycle f sw = 300khz - - 0 % fb pin bias current -80- na undervoltage protection v uv fraction of the set point; ~3s noise filter 75 - 85 % overvoltage protection v ovp fraction of the set point; ~1s noise filter 112 - 120 % oscillator free running frequency rt = vcc5, t a = -40c to +85c 270 300 330 khz total variation t a = -40c to +85c, with frequency set by external resistor at rt - 10% - % frequency range (set by rt) vin = 12v 100 - 1400 khz isl6420b
8 fn6901.1 december 4, 2009 ramp amplitude (note 10) v osc -1.25- v p-p reference and soft-start/enable internal reference voltage v ref 0.594 - 0.606 v soft-start current i ss -10- a soft-start threshold v soft 1.0 - - v enable low (converter disabled) --1.0v pwm controller gate drivers gate drive peak current -0.7- a rise time co = 1000pf - 20 - ns fall time co = 1000pf - 20 - ns dead time between drivers - 20 - ns error amplifier dc gain (note 10) -88- db gain-bandwidth product (note 10) gbw - 15 - mhz slew rate (note 10) sr - 6 - v/s comp souce/sink current (note 10) 0.4 ma overcurrent protection ocset current source i ocset v ocset = 4.5v 80 100 120 a power-good and control functions power-good lower threshold v pg- fraction of the set point; ~3s noise filter -14 -10 -8 % power-good higher threshold v pg+ fraction of the set point; ~3s noise filter 9-16% pgood leakage current i pglkg v pullup = 5.0v (note 11) - - 1 a pgood voltage low i pgood = 4ma - - 0.5 v pgood delay cdel = 0.1f - 125 - ms cdel current for pgood cdel threshold = 2.5v - 2 - a cdel threshold -2.5- v external reference min external refe rence input at gpio1/refin v mset/mode = h, c refout = 2.2f - 0.600 - v max external reference input at gpio1/refin v mset/mode = h, c refout = 2.2f - - 1.250 v reference buffer buffered output voltage - internal reference v refout i refout = 1ma,v mset/mode = high, c refout = 2.2f, t a = -40c to +85c 0.583 0.595 0.607 v buffered output voltage - internal reference v refout i refout = 20ma,v mset/mode = high, c refout = 2.2f, t a = -40c to +85c 0.575 0.587 0.599 v electrical specifications operating conditions: vin = 12v, pvcc shorted with vcc5, t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 12) typ max (note 12) units isl6420b
9 fn6901.1 december 4, 2009 buffered output voltage - external reference v refout v refin = 1.25v, i refout = 1ma, vmset2/mode = high, c refout = 2.2f 1.227 1.246 1.265 v buffered output voltage - external reference v refout v refin = 1.25v, i refout = 20ma, vmset2/mode = high, c refout = 2.2f 1.219 1.238 1.257 v current drive capability c refout = 2.2f 20 - - ma voltage margining voltage margining range (note 10) -10 - +10 % cdel current for voltage margining -100- a slew time cdel = 0.1f, vmset = 330k -2.5- ms iset1 on fb pin vmset = 330k, gpio1 = l gpio2 = h -7.48- a iset2 on fb pin vmset = 330k, gpio1 = h gpio2 = l -7.48- a thermal shutdown shutdown temperature (note 10) -150- c thermal shutdown hysteresis (note 10) -20- c notes: 7. the operating supply current and shutdo wn current specifications for 5v inpu t are the same as vin supply current specifications, i.e., 5.6v to 28v input conditions. these should al so be tested with part configured for 5v input configuration , i.e., vin = vcc5 = pvcc = 5v. 8. this is the v cc current consumed when the device is active but not switching. does not include gate drive current. 9. when the input voltage is 5.6v to 28v at vin pin, the vcc5 pin provides a 5v output capable of 50ma (max) total from the internal ldo. when the input voltage is 5v , vcc5 pin will be us ed as a 5v input, the internal ldo regulator is disabled and the vin must be connected to the vcc5. in both cases the pvcc pin should always be connected to vcc5 pin (refer to ?pin descriptions? on page 11 for more details). 10. limits established by characterization and are not production tested. 11. it is recommended to use vcc5 as the pull-up source. 12. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications operating conditions: vin = 12v, pvcc shorted with vcc5, t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 12) typ max (note 12) units isl6420b
10 fn6901.1 december 4, 2009 typical performance curves figure 1. v ref vs temperature figure 2. v sw vs temperature figure 3. i ocset vs temperature figure 4. efficiency vs v in figure 5. figure 6. 0.604 0.602 0.600 0.598 0.596 0.594 -40 60 -15 10 35 85 temperature (c) v ref (v) 320 310 300 290 280 270 -40 60 -15 10 35 85 temperature (c) f sw (khz) 1.15 1.05 0.95 0.85 -40 60 -15 10 35 85 temperature (c) i ocset normalized 80 82 84 86 88 90 92 94 01020 30 v in (v) efficiency (%) 51525 i out = 5a +25c, vin = 28v, i in = 1.367, i out = 10a isl6420b
11 fn6901.1 december 4, 2009 pin descriptions vin this pin powers the controller and must be decoupled to ground using a ceramic capacitor as close as possible to the vin pin. sgnd this pin provides the signal ground for the ic. tie this pin to the ground plane through the lowest impedance connection. lgate this pin provides the pwm- controlled ga te drive for the lower mosfet. phase this pin is the junction point of the output filter inductor, the upper mosfet source and the lower mosfet drain. this pin is used to monitor the voltage drop across the upper mosfet for overcurrent protection. this pin also provides a return path for the upper gate drive. ugate this pin provides the pwm- controlled ga te drive for the upper mosfet. boot this pin powers the upper mosfet driver. connect this pin to the junction of the bootstrap capacitor and the cathode of the bootstrap diode. the anode of the bootstrap diode is connected to the pvcc pin. fb this pin is connected to the feedback resistor divider and provides the voltage feedback signal for the controller. this pin sets the output voltage of the converter. comp this pin is the error amplifier output pin. it is used as the compensation point for the pwm error amplifier. pgood this pin provides a power good status. it is an open collector output used to indicate the status of the output voltage. rt this is the oscillator frequency selection pin. connecting this pin directly to vcc5 will select the oscillator free running frequency of 300khz. by placing a resistor from this pin to gnd, the oscillator frequency can be programmed from 100khz to 1.4mhz. figure 8 shows the oscillator frequency vs. the rt resistance. figure 7. efficiency vs load current (v out = 3.3v) typical performance curves (continued) 80 82 84 86 88 90 92 94 96 98 012345678910 load (a) efficiency (%) v in = 12v v in = 5v table 1. input supply configuration input pin configuration 5.5v to 28v connect the input to the vin pin. the vcc5 pin will provide a 5v output from the internal ldo. connect pvcc to vcc5. 5v 10% connect the input to the vcc5 pin. connect the pvcc and vin pins to vcc5. 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 0 25 50 75 100 125 150 rt (k ) frequency (khz) figure 8. oscillator frequency vs rt isl6420b
12 fn6901.1 december 4, 2009 cdel the pgood signal can be delayed by a time proportional to a cdel current of 2a and the value of the capacitor connected between this pin and ground. a 0.1f will typically provide 125ms delay. when in the voltage margining mode, the cdel current is 100a typical and provides the delay for the output voltage slew rate, 2.5ms typical for the 0.1f capacitor. pgnd this pin provides the power ground for the ic. tie this pin to the ground plane through the lowest impedance connection. pvcc this pin is the power connection for the gate drivers. connect this pin to the vcc5 pin. vcc5 this pin is the output of the internal 5v ldo. connect a minimum of 4.7f ceramic decoupling capacitor as close to the ic as possible at this pin. refer to table 1. enss this pin provides enable/disable function and soft-start for the pwm output. the output drivers are turned off when this pin is held below 1v. ocset connect a resistor (r ocset ) and a capacitor from this pin to the drain of the upper mosfet. r ocset , an internal 100a current source (i ocset ), and the upper mosfet on resistance r ds(on) set the converter overcurrent (oc) trip point. gpio1/refin this is a dual function pin. if vmset/mode is not connected to vcc5 then this pin serves as gpio1. refer to table 3 for gpio commands interpretation. to use gpio1/refin as input reference, connect vmset/mode to vcc5 and gpio2 to sgnd. connect the desired reference voltage to the gpio1/refin pin in the range of 0.6v to 1.25v. connect gpio1/refin and vmset/mode pins to vcc5, gpio2 to sgnd, the ic operates with the internal reference and no voltage margining function. refout it provides buffered reference output for refin. connect 2.2f decoupling capacitor to this pin. vmset/mode this pin is a dual function pin. tie this pin to vcc5 to disable voltage margining. wh en not tied to vcc5, this pin serves as vmset. connect a resistor from this pin to ground to set delta for voltage margining. if voltage margining and external reference tracking mode are not needed, vnset/mode, gpio1/refin and gpio2 all together can be tied directly to ground. gpio2 this is general purpose io pin for voltage margining. refer to table 3. exposed thermal pad this pad is electrically isolated. connect this pad to the signal ground plane using at least five vias for a robust thermal conduction path. table 2. voltage margining/ddr or tr acking supply pin configuration function/modes pin configurations vmset/mode refout gpio1/refin gpio2 enable voltage margining pin connected to gnd with resistor. it is used as vmset. connect a 2.2f capacitor for bypass of external reference. serves as a general purpose i/o. refer to ta b l e 3 . serves as a general purpose i/o. refer to ta b l e 3 . no voltage margining. normal operation with inte rnal reference. buffered v refout = 0.6v. h connect a 2.2f capacitor to gnd. h (note 14) l no voltage margining. external reference. buffered v refout =v refin h connect a 2.2f capacitor to gnd. connect to an external reference voltage source (0.6v to 1.25v) l notes: 13. the gpio1/refin and gpio2 pi ns cannot be left floating. 14. ensure that gpio1/refin is tied high prior to the logic change at vmset/mode. isl6420b
13 fn6901.1 december 4, 2009 functional description initialization the isl6420b automatically in itializes upon receipt of power. the power-on reset (por) function monitors the internal bias voltage generated from ldo output (vcc5) and the enss pin. the por function initiates the soft-start operation after the vcc5 exceeds the por threshold. the por function inhibits operation with the chip disabled (enss pin <1v). the device can operate from an input supply voltage of 5.5v to 28v connected directly to the vin pin using the internal 5v linear regulator to bias the chip and supply the gate drivers. for 5v 10% applications, connect vin to vcc5 to bypass the linear regulator. soft-start/enable the isl6420b soft-start function uses an internal current source and an external capacitor to reduce stresses and surge current during start-up. when the output of the internal linear regulator reaches the por threshold, the por function initiates the soft-start sequence. an internal 10a current source charges an external capacitor on the enss pin linearly from 0v to 3.3v. when the enss pin voltage reaches 1v typically, the internal 0.6v reference begins to charge following the dv/dt of the enss voltage. as the soft-start pin charges from 1v to 1.6v, the reference voltage charges from 0v to 0.6v. figure 9 shows a typical soft-start sequence. overcurrent protection the overcurrent function pr otects the converter from a shorted output by us ing the upper mosfet?s on-resistance, r ds(on) to monitor the current. this method enhances the converter?s efficiency and reduces cost by eliminating a current sensing resistor. the overcurrent function cycl es the soft-start function in a hiccup mode to provide fault protection. a resistor connected to the drain of the upper fet and the ocset pin programs the overcurrent trip level. the phase node voltage will be compared against the voltage on the ocset pin, while the upper fet is on. a current (100a typically) is pulled from the ocset pin to establish the ocset vo ltage. if phase is lower than ocset while the uppe r fet is on then an overcurrent condition is detected for that clock cycle. the upper gate pulse is i mmediately terminated, and a counter is incremented. if an overcurrent condition is detected for 8 consecutive clock cycles, and the circuit is not in soft-start, the isl6420b enters into the soft-start hiccup mode. during hiccup, the external capacitor on the enss pin is discharged. after the capacitor is discharged, it is released and a soft-start cycle is initiated. there are three dummy soft-start delay cycles to allow the mosfets to cool down, to keep the average po wer dissipation in hiccup mode at an acceptable level. at the fourth soft-start cycle, the output starts a normal soft-start cycle, and the output tries to ramp. during soft-start, pulse term ination current limiting is enabled, but the 8-cycle hiccup counter is held in reset until soft-start is completed. figure 10 shows the overcurrent hiccup mode. the overcurrent function will trip at a peak inductor current (i oc ) determined from equation 1, where i ocset is the internal ocset current source. the oc trip point varies mainly due to the upper mosfets r ds(on) variations. to avoid overcurrent tripping in the normal oper ating load range, find the r ocset resistor from equation 1 with: table 3. voltage margining controlled by gpio1 and gpio2 gpio1 gpio2 vout l l no change lh+ vout hl- vout hhignored figure 9. typical soft-start waveform v in = 28v, v out = 3.3v, i out = 10a figure 10. typical overcurrent hiccup mode v out i out phase enss i oc i ocset r ocset ? r ds on () --------------------------------------------------- = (eq. 1) isl6420b
14 fn6901.1 december 4, 2009 1. the maximum r ds(on) at the highest junction temperature. 2. determine , where i is the output inductor ripple current. a small ceramic capacitor should be placed in parallel with r ocset to smooth the voltage across r ocset in the presence of switching noise on the input voltage. voltage margining the isl6420b has a voltage margining mode that can be used for system testing. the voltage margining percentage is resistor selectable up to 10%. the voltage margining mode can be enabled by connecting a margining set resistor from vmset pin to ground and using the control pins gpio1/2 to toggle between positive and negative margining (refer to table 3). with voltage margining enabled, the vmset resistor to ground will set a current, which is switched to the fb pin. the current will be equa l to 2.468v divided by the value of the external resist or tied to the vmset pin. use a resistor in the range of 150k to 400k for vmset resistor. the power supply output increases when gpio2 is high and decreases when gp io1 is high. the amount that the output voltage of the power supply changes with voltage margining, will be equal to 2.468v x the ratio of the external feedback resistor and the external resistor tied to vmset. figure 11 shows the positive and negative margining for a 3.3v output, using a 20.5k feedback resistor and using various vmset resistor values. i oc for i oc i out max () i () 2 ? + > i vm 2.468v r vmset ----------------------- - = (eq. 2) v vm 2.468v r fb r vmset ----------------------- - = (eq. 3) 2.8 2.9 3.1 3.2 3.3 3.4 3.5 3.6 3.7 150 175 200 225 250 275 300 325 350 375 400 rvmset (k ) v out (v) 3.0 figure 11. voltage margining vs. vmset resistance figure 12a. figure 12b. figure 13. pgood delay v in = 12v, v out = 3.3v, no load vin = 12v, v out = 3.3v, no load v in = 12v, v out = 3.3v, no load v in = 12v, v out = 3.3v, i out = 10a isl6420b
15 fn6901.1 december 4, 2009 the slew time of the current is set by an external capacitor on the cdel pin, which is charged and discharged with a 100a current source. the change in voltage on the capacitor is 2.5v. this same capacitor is used to set the pgood active delay after soft-start. when pgood is low, the internal pgood circuitry uses the capacitor and when pgood is high, the voltage margining circuit uses the capacitor. the slew time for voltage margining can be in the range of 300s to 2ms. external reference/ddr supply the voltage margining can be disabled by connecting the vmset/mode to vcc5. in this mode, the chip can be configured to work with an external reference input and provide a buffered reference output. if vmset/mode pin and the gpio1/refin pin are both tied to vcc5, then the internal 0.6v reference is used as the error amplifier non-in verting input. the buffered reference output on refout will be 0.6v 0.01v, capable of sourcing 20ma and sinking up to 50a current with a 2.2f capacitor connected to the refout pin. if the vmset/mode pin is tied to high but gpio1/refin is connected to an external voltage source between 0.6v to 1.25v, then this external voltage is used as the reference voltage at the positive input of the error amplifier. the buffered reference output on refout will be vrefin 0.01v, capable of sourcing 20ma and sinking up to 50a current with a 2.2f capacitor on the refout pin. power-good the pgood pin can be used to monitor the status of the output voltage. pgood will be true (open drain) when the fb pin is within 10% of the reference and the enss pin has completed its soft-start ramp. additionally, a capacitor on the cdel pin will set a delay for the pgood signal. after the enss pin completes its soft-start ramp, a 2a current begins charging the cdel capacitor to 2.5v. the capacitor will be quickly discharged before pgood goes high. the programmable delay can be used to sequence multiple converters or as a low-true reset signal. if the voltage on the fb pin exceeds 10% of the reference, then pgood will go low after 1s of noise filtering. over-temperature protection the ic is protected against over-temperature conditions. when the junction temperature exceeds +150c, the pwm shuts off. normal operation is resumed when the junction temperature is cooled down to +130c. shutdown when enss pin is below 1v, the regulator is disabled with the pwm output drivers tri-stated. when disabled, the ic power will be reduced. undervoltage if the voltage on the fb pin is less than 15% of the reference voltage for 8 consecutive pwm cycles, then the circuit enters into soft-start hiccup mode. this mode is identical to the overcurrent hiccup mode. overvoltage protection if the voltage on the fb pin exceeds the reference voltage by 15%, the lower gate driver is turned on continuously to discharge the output voltage. if the overvoltage condition continues for 32 consecutive pwm cycles, then the chip is turned off with the gate drivers tri-stated. the voltage on the fb pin will fall and reach the 15% undervol tage threshold. after 8 clock cycles, the chip will enter soft-start hiccup mode. this mode is identical to the overcurrent hiccup mode. gate control logic the gate control logic translates generated pwm control signals into the mosfet gate drive signals providing necessary amplification, level shifting and shoot-through protection. also, it has functions that help optimize the ic performance over a wide range of operational conditions. since mosfet switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower mosfets. the lower mosfet is not turned on until the gate-to-source voltage of the upper mosfet has decreased to less than approximately 1v. similarly, the upper mosfet is not turned on until the gate-to-source voltage of the lower mosfet has decreased to less than approximately 1v. this allows a wide variety of upper and lower mosfets to be used without a concern for simultaneous conduction, or shoot-through. start-up into pre-biased load the isl6420b is designed to power-up into a pre-biased load. this is achieved by transitioning from diode emulation mode to a forced continuous conduction mode during start-up. the lower gate turns on for a short period of time and the voltage on the phase pin is sensed. when this goes negative the lower gate is turned off and remains off till the next cycle. as a result, the inductor current will not go negative during soft-start and thus will not discharge the pre-biased load. the wavefo rm for this condition is shown in figure 14. isl6420b
16 fn6901.1 december 4, 2009 application guidelines layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close together as possible using ground plane construction or single point grounding. figure 15 shows the critical power components of the converter. to minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. the components shown in figure 15 should be located as close together as possible. please note that the capacitors c in and c o each represent numerous physical capacitors. locate the isl6420b within 3 inches of the mosfets, q 1 and q 2 . the circuit traces for the mosfets? gate and source connections from the isl6420b must be sized to handle up to 1a peak current. figure 16 shows the circuit traces that require additional layout consideration. use single point and ground plane construction for the circuits shown. minimize any leakage current paths on the ss pin and locate the capacitor, c ss close to the ss pin because the internal current source is only 10a. provide local v cc decoupling between vcc and gnd pins. locate the capacitor, c boot as close as practical to the boot and phase pins. feedback compensation figure 17 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (v out ) is regulated to the reference voltage level. the error amplifier (error amp) output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse-width modulated (pwm) wave with an amplitude of vin at the phase node. the pwm wave is smoothed by the output filter (l o and c o ). the modulator transfer function is the small-signal transfer function of v out /v e/a . this function is dominated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (vin) divided by the peak-to-peak oscillator voltage v osc . figure 14. prebiased output at 25ma load v in = 12v, v out = 3.3v at 25ma load gnd l o c o lgate ugate phase q1 q2 d2 figure 15. printed ci rcuit board power and ground planes or islands vin v out return isl6420b c in load figure 16. printed circuit board small signal layout guidelines +5v isl6420b enss gnd v cc boot d 1 l o c o v out load q 1 q 2 phase +vin c boot c vcc c ss isl6420b
17 fn6901.1 december 4, 2009 modulator break frequency equations the compensation network consists of the error amplifier (internal to the isl6420b) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180. the following equations relate the compensation network?s poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figure 17. use the following guidelines for locating the poles and zeros of the compensation network. compensation break frequency equations 1. pick gain (r2/r1) for desired converter bandwidth 2. place 1 st zero below filter?s double pole (~75% f lc ) 3. place 2 nd zero at filter?s double pole 4. place 1 st pole at the esr zero 5. place 2 nd pole at half the switching frequency 6. check gain against erro r amplifier?s open-loop gain 7. estimate phase margin - repeat if necessary figure 18 shows an asymptotic plot of the dc/dc converter?s gain vs. frequency. the actual modulator gain has a high gain peak due to the high q factor of the output filter and is not shown in figure 18. using the previously mentioned guidelines should give a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the error amp lifier. the loop gain is constructed on the log-log graph of figure 18 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. figure 17. voltage - mode buck converter compensation design v out osc reference l o c o esr vin v osc error amp pwm driver (parasitic) - ref r 1 r 3 r 2 c 3 c 2 c 1 comp v out fb z fb isl6420b z in comparator driver detailed compensation components phase v e/a + - + - z in z fb + v out v ref 1 r 1 r 4 ------ - + ?? ?? ?? = r 4 f lc 1 2 l o c o ? ? -------------------------------------- - = (eq. 4) f esr 1 2 esr c o ? () ? -------------------------------------------- - = (eq. 5) f z1 1 2 r ? 2c1 ? ---------------------------------- = (eq. 6) f p1 1 2 r2 ? c1 c2 ? c1 c2 + ---------------------- ?? ?? ? ------------------------------------------------------ - = (eq. 7) f z2 1 2 r1 r3 + () c3 ? ? ----------------------------------------------------- - = (eq. 8) f p2 = 1 2 r3 c3 ? ? ---------------------------------- (eq. 9) 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 f lc f esr compensatio n gain (db) frequency (hz) gain 20log (vin/ v osc ) modulator gain 20log (r 2 /r 1 ) closed loop gain figure 18. asymptotic bode plot of converter gain isl6420b
18 fn6901.1 december 4, 2009 the compensation gain uses external impedance networks z fb and z in to provide a stable, high bandwidth (bw) overall loop. a stable control loop has a gain crossing with -20db/decade slope and a phase margin greater than 45. include worst case component variations when determining phase margin. component selection guidelines output capacitor selection an output capacitor is required to filter the output and supply the load transient current. the filtering requirements are a function of the switching frequency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern microprocessors produce transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. for example, intel recommends that the high frequency decoupling for the pentium pro be composed of at least forty (40) 1.0f ceramic capacitors in the 1206 surface-mount package. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor's esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transients. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current and the output capacitors esr. the ripple voltage and current are approximated by equations 10 and 11: increasing the value of inductance reduces the ripple current and voltage. however, larger inductance values reduce the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fast control loop design, the isl6420b will pr ovide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transient current level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the re moval of load. equations 12 and 13 give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. with a +5v input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q 1 turns on. place the small ceramic capacitors physically close to the mo sfets and between the drain of q 1 and the source of q 2 . the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 x greater than the maximum input voltage and a voltage rating of 1.5 x is a conservative guideline. the rms current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the dc load current. equation 14 i l v in - v out fs x l ------------------------------- - v out v in --------------- - ? = (eq. 10) v out i l esr ? = (eq. 11) t rise l o i tran v in v out ? ------------------------------- - = (eq. 12) t fall l o i tran v out ------------------------------ - = (eq. 13) isl6420b
19 fn6901.1 december 4, 2009 shows a more specific formula for determining the input ripple: for a through hole design, several electrolytic capacitors (panasonic hfq series or nichicon pl series or sanyo mv-gx or equivalent) may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. the tps series available from avx, and the 593d series from sprague are both surge current tested. mosfet selectio n/considerations the isl6420b requires 2 n-channel power mosfets. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty factor (see equations 15 and 16). only the upper mosfet has switching losses, since the schottky rectifier clamps the switching node before the synchronous rectifier turns on. where d is the duty cycle = vo/vin, t sw is the switching interval, and f sw is the switching frequency. these equations assume linear voltage-current transitions and do not adequately model power loss due the reverse recovery of the lower mosfet?s body diode. the gate-charge losses are dissipated by the isl6420b and don't heat the mosfets. however, large gate-charge increases the switching interval, t sw which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient te mperature and air flow. schottky selection rectifier d 2 is a clamp that catches the negative inductor swing during the de ad time between turning off the lower mosfet and turning on the upper mosfet. the diode must be a schott ky type to prevent the parasitic mosfet body diod e from conducting. it is acceptable to omit the diode and let the body diode of the lower mosfet clamp the negative inductor swing, but efficiency will drop one or two percent as a result. the diode's rated reverse breakdown voltage must be greater than the maximum input voltage. i rms i max dd 2 ? () ? = (eq. 14) p ufet i o 2 r ds on () d 1 2 -- - i o v in t sw f sw ??? + ?? = (eq. 15) p lfet i o 2 r ds on () 1d ? () ?? = (eq. 16) isl6420b
20 fn6901.1 december 4, 2009 isl6420b package outline drawing l20.4x4 20 lead quad flat no-lead plastic package rev 1, 11/06 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view bottom view side view 4.00 a 4.00 b 6 pin 1 index area (4x) 0.15 4x 0.50 2.0 16x 20 16 15 11 pin #1 index area 6 2 . 10 0 . 15 5 1 0.25 +0.05 / -0.07 0.10 m ab c 20x 0.6 +0.15 / -0.25 4 6 10 base plane seating plane 0.10 see detail "x" 0.08 c c c 0 . 90 0 . 1 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 6 typ ) ( 2. 10 ) ( 20x 0 . 8) ( 20x 0 . 5 ) ( 20x 0 . 25 )
21 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6901.1 december 4, 2009 for additional products, see www.intersil.com/product_tree isl6420b shrink small outline plastic packages (ssop) quarter size outline plastic packages (qsop) notes: 1. symbols are defined in the ?m o series symbol list? in sec- tion 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not includ e mold flash, protrusions or gate burrs. mold flash, protru sion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not includ e interlead flash or protru- sions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the cross- hatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are sh own for reference only. 9. dimension ?b? does not incl ude dambar protrusion. allow- able dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches . converted mi llimeter di- mensions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m20.15 20 lead shrink small outline plastic package (0.150? wide body) sym- bol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - a2 - 0.061 -1.54- b 0.008 0.012 0.20 0.30 9 c 0.007 0.010 0.18 0.25 - d 0.337 0.344 8.56 8.74 3 e 0.150 0.157 3.81 3.98 4 e 0.025 bsc 0.635 bsc - h 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 l 0.016 0.050 0.41 1.27 6 n20 207 0 8 0 8 - rev. 1 6/04

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